1. Field of the Invention
This invention relates to methods for compacting test sets for sequential circuits. More specifically, to partitioning and reordering methods for fast static test sequence compaction of sequential circuits.
This application relates to U.S. application Ser. No. 09/001,543 filed on Dec. 31, 1997 entitled, "State Relaxation Based Subsequence Removal Method for Fast Static Compaction in Sequential Circuits," which is assigned to the Assignee of the present invention and which is incorporated herein by reference.
2. Background and Description of Related Art
Since the cost of testing sequential circuits is directly proportional to the number of test vectors in a test set, short test sequences are desirable. Reduction in test set size can be achieved using static or dynamic test set compaction algorithms. Dynamic techniques such as those described in Chakradhar, S., et al., "Bottleneck Removal Algorithm for Dynamic Compaction and Test Cycle Removal," Proc. European Design Automation Conf., pp. 98-104, September 1995), Chakradhar, S., et al., "Bottleneck Removal Algorithm for Dynamic Compaction in Sequential Circuits," IEEE Trans. on Computer-Aided Design, (Accepted for Publication) 1997 and Niermann, T. M., et al., "Method for Automatically Generating Test Vectors for Digital Integrated Circuits," U.S. Pat. No. 5,377,197, 1994, perform compaction concurrently with the test generation process. These techniques often require modification of the test generator.
Static compaction techniques, on the other hand, are employed after the test generation process. Obviously, static techniques are independent of the test generation algorithm and do not require modifications to the test generator. In addition, static compaction techniques can further reduce the size of test sets obtained after dynamic compaction.
Several static compaction approaches for sequential circuits have been proposed in the following papers: Niermann, T. M., et al. "Test Compaction for Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 260-67, February 1992, So, B., "Time-efficient Automatic Test Pattern Generation System," Ph.D. Thesis, EE Dept. Univ. of Wisconsin-Madison, 1994, Pomeranz, I., et al., "On Static Compaction of Test Sequences for Synchronous Sequential Circuits," Proc. Design Automation Conf., pp. 215-20, June 1996 and Hsiao, M. S. et al., "Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors," Proc. IEEE VLSI Test Symp., pp. 188-195, April 1995.
Some of these approaches (Niermann, Time Compaction, So) cannot reduce test sets produced by random or simulation-based test generators. Static compaction techniques based on vector insertion, omission, or selection have also been investigated (Pomeranz). These techniques require multiple fault simulation passes. If a vector is omitted or swapped, the fault simulator is invoked to make sure that the fault coverage is not affected. Vector restoration techniques, as described in Guo, R., et al., "Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration," Technical Report Aug. 3, 1997, Electrical and Computer Engineering Department, University of Iowa, August 1997, aim to restore sufficient vectors necessary to detect all faults, starting with the harder faults. Fast static test set compaction based on removing recurrence subsequences that start and end on the same states has also been reported recently (Hsiao). However, these test sets are not as compact as those achieved by algorithms that use multiple fault simulation passes.